Dylan Patel, an analyst at the semiconductor industry analysis agency SemiAnalysis, said that Apple is shifting its embedded chip core instruction set from the ARM architecture to the RISC-V architecture, and Google will also apply the SiFive X280 on the TPU.
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For example, the existing Apple A15 Bionic chip has more than a dozen Arm-based CPU cores distributed on the chip for various functions that are not directly user-facing. SemiAnalysis can confirm that these cores are actively moving to the RISC-V architecture in future generations of hardware.
Some people also pointed out that RISC-V, as an open source hardware architecture in BSD, according to Apple’s consistent style of behavior, will not use RISC-V directly, and it will be closed source after magic modification (may be named Apple ISA ) with its own closed-source system for overall marketing, similar to the instruction set mode in the CPU after A10.
In the Apple Silicon design, the core is a very important part. For example, in the M1, there are more than 30 cores responsible for various workloads that are not related to the system, such as WiFi/Bluetooth, interface retiming, touchpad control, cores for NAND chips, etc., they all have their own firmware and provide support for SoC peripheral function circuits.
At present, most of these cores are based on Arm M-series or low-end A-series IP, and Apple is currently looking for ways to replace these cores with RISC-V. Given that a large portion of the software relies on the main big to run, other minor SoC tasks migrate to the heterogeneous ISA with only a few firmware tweaks. More importantly, Apple can save a huge amount of licensing fees with this. According to Cook’s thinking, there is no reason for Apple not to do it.
